Oxide tunneling current in metal oxide silicon (MOS) field effect transistors (FET) is a non-negligible component of power consumption as gate oxides get thinner, and may in the future become the dominant leakage mechanism in sub-100 nm CMOS circuits. The gate current is dependent on various conditions and three main static regions of operation may be identified for a MOSFET. The amount of gate-leakage current differs by several orders of magnitude from one region to another. Whether a transistor leaks significantly or not is also affected by its position in relation to other transistors within a CMOS circuit structure, as this affects the voltage stress to which a particular device is subjected.
The three regions of operation are functions of applied bias if one only considers the parameters that affect the magnitude of gate-leakage current in one MOSFET as it operates in relation to other MOSFETs. Assuming that the supply voltage (Vdd) and the threshold voltage (Vt) are fixed, then a MOSFET in a static CMOS logic gate operates in one of the three regions.
The first region is called “strong inversion” and is the region where a MOSFET operates with the absolute value of the gate to source voltage (|VGS|) equal to Vdd. The gate-leakage current density for an N-channel FET (NFET) in strong inversion may be as high as 103 amperes (A)/square centimeter (cm2) for an oxide thickness of 1.5 nanometers (nm) at a Vdd equal to 3 volts (V). For such a thin oxide, a more realistic operational value for Vdd is 1.2 V, in which case the gate-leakage current would more likely be around 20 A/cm2.
The second region is called the “threshold” region where |VGS|=Vt. A MOSFET operating in the threshold region will have a gate-leakage current significantly less than one operating in the strong inversion region, typically 3 to 6 orders of magnitude less depending on Vdd and the oxide thickness.
The third region is called the “OFF” region where |VGS|=0.0 V. For an NFET operating in the OFF region, there is no leakage if the drain voltage (Vd)=0.0 V. However, if Vd is equal to Vdd, then a small gate-leakage current in the reverse direction (drain to gate) may be present due to gate-drain overlap area. Of course, this current depends on transistor geometry and is typically 10 orders of magnitude less than the gate-leakage current in the strong inversion region.
The above three regions represent three distinct conditions or states for the channel of a MOSFET. Whether an “ON” FET operates at strong inversion or at threshold is determined by its position inside a logic circuit structure as well as by the state of other FETs in the circuit structure.
Both NFETs and P-channel FETs (PFETs) in a logic circuit structure operate in one of the three regions described above. However, the main tunneling current in a PFET device in strong inversion is due to hole tunneling from the valence band, and the main tunneling current in an NFET device in strong inversion is due to electron tunneling from the conduction band. Because of this, PFET gate-leakage currents are about 10 times smaller than equivalent sized NFET devices. This fact is important in assessing gate-leakage in a static CMOS circuit.
Another component of leakage current is called sub-threshold leakage current. This current flows from the drain to the source of a FET when the gate is below the threshold voltage. This component of leakage is not a function of gate oxide thickness but is primarily a function of the gate width, the device threshold voltage and the power supply voltage. Sub-threshold leakage may be reduced by reducing gate width, increasing the threshold voltage or reducing the power supply voltage. For a given technology family, it is assumed that the power supply voltage has been reduced to a required level to minimize dynamic switching power. Likewise the gate width is reduced as a result of reducing device sizes. To minimize sub-threshold power below the limit established by these parameters requires some type of power supply voltage management within particular circuits.
As CMOS circuits become smaller, gate-leakage current of the FETs may become a significant factor in power dissipation. Leakage power may ultimately become the limiting factor in determining how small practical FET devices may be manufactured. As FET devices are made smaller, the power supply voltage is correspondingly reduced. However, this may not achieve an adequate reduction in leakage power dissipation. Alternate techniques are being employed to reduce gate-leakage power.
To reduce sub-threshold leakage power supply management techniques may be used wherein the supply voltage is degated and thus reduced to zero for particular devices. This technique is referred to as power-gating and isolates the power supply voltage in groups of circuits at controlled times. Since this may cause a loss of a logic state additional action may be necessary. These circuits are sometimes referred to as being part of a power-gated or “cuttable” domain. Other circuits may be evaluating a logic function and may not be in a power-gated domain. Interfacing circuits from a power-gated domain to circuits in a non-power-gated domain may require methods to ensure logic states are preserved. The logic state of an output from a power-gated domain may become uncertain during the time period of power-gating. While the benefits of power-gating are known, there is no consensus on strategies to preserve logic states of outputs in the power-gated domains. Since power-gated domains may be variably applied, the method of preserving output logic states from circuits in a power-gated domain should be controlled by the power-gating control signals themselves.
There is, therefore, a need for a circuit methodology for designing CMOS circuits that allows the variable use of power-gating to reduce sub-threshold leakage while preserving the output states of outputs interfacing between power-gated domains and non-power-gated domains.